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1/34 STW5093 march 2004 features: complete codec and filter system including: 14 bit linear analog to digital and digital to analog converters. 8 bit companded analog to digital and digital to analog converters a- law or -law. transmit and receive band-pass filters active antialias noise filter. phone features: one microphone biasing output remote control (remocon) function three switchable microphone amplifier inputs. gain programmable:0 . . 42.5 db amplifier, 1.5 db steps (+ mute). earpiece audio output. attenuation programmable: 0 . . 30 db, 2 db steps. external audio output. attenuation programmable: 0 . . 30 db, 2 db steps. driving capability: 140mw over 8 ? transient supression signal during power on and during amplifier switching. internal programmable sidetone circuit. attenuation programmable: 16 db range, 1 db step. internal ring, tone and dtmf generator, sinewave or squarewave waveforms. attenuation programmable: 27db range, 3db step. three frequency ranges: a) 3.9hz . . . . 996hz, 3.9hz step b) 7.8hz . . . . 1992hz, 7.8hz step c) 15.6hz . . . . 3984hz, 15.6hz step programmable pulse width modulated buzzer driver output. general features: single 2.7v to 3.3v supply extended temperature range operation (*) -40c to 85c. 1.0 w standby power (typ. at 2.7v). 13mw operating power (typ. at 2.7v). 1.8v to 3.3v cmos compatible digital interfaces. programmable pcm and control interface microwire compatible. applications: gsm/dcs1800/pcs1900/jdc digital cellular telephones. cdma cellular telephones. dect/ct2/phs digital cordless telephones. battery operated audio front-ends for dsps. (*) functionality guaranteed in the range - 40c to +85c; timing and electrical specifications are guaranteed in the range - 30c to +85c. general description STW5093 is a high performance low power combined pcm codec/filter device tailored to implement the audio front-end functions required by low voltage/low power consumption digital cellular terminals. STW5093 offers a number of programmable functions accessed through a serial control channel that easily interfaces to any classical microcontroller. the pcm interface sup- ports both non-delayed (normal and reverse) and de- layed frame synchronization modes. STW5093 can be configurated either as a 14-bit lin- ear or as an 8-bit companded pcm coder. additionally to the codec/filter function, STW5093 includes a tone/ring/dtmf generator, a sidetone gen- eration, and a buzzer driver output.STW5093 fulfills and exceeds d3/d4 and ccitt recommendations and etsi requirements for digital handset terminals. main applications include digital mobile phones, as cellular and cordless phones, or any battery powered equipment that requires audio codecs operating at low single supply voltages. tssop30 ordering number: STW5093 2.7v supply 14-bit linear codec with high-performance audio front-end .com .com .com 4 .com u datasheet
STW5093 2/34 pin connections (top view) block diagram v cc remout remin mic3+ v ccp vlr+ vlr- gndp lo vfr dx dr fs mclk 1 3 2 4 13 14 15 28 27 18 17 16 29 30 d98tl399 gnda mic2- mic2+ bz cs- cclk 10 11 12 21 20 19 mic1- ci 922 mic3- mic1+ v cca auxclk gnd vccio 5 7 8 26 24 23 mbias co 625 vs & te mic preamp 0/20db + mute mic amp 0 -> 22.5 1.5db step de (a) (b) tx filter pcm adc rx filter pcm dac transmit register remocon ren,rlm,roi,rdl receive register 6db -1 1 12db oe tone, ring & dtmf gener. & filter eara output 0 -> -30db, 2db step exta output rte se si tone amp 0 -> -27db 3db step sidetone amp -12.5 -> -27.5db 1db step control interface -wire clock generator & synchronizer interface latch buzzer driver be en gndp gnda gnd vcca vcc vccp level adjust (pwm) mic3- mic2- mic1- mic2+ mic1+ mic3+ vfr vlr- vlr+ dx remout remin co dr ci cs- cclk fs mclk lo bz d98tl408 pg microphone bias mbias hpb vccio aux clk slc mb .com .com .com .com 4 .com u datasheet
3/34 STW5093 pin function n pin description 1v cc power supply input for the digital section. 2 remout remocon function digital output. 3 remin remocon function input. an high level at this pin is detected as a non pressed key, while a low level is detected as a pressed key. 4 mic3+ third positive high impedance input to transmit preamplifier for microphone connection. 5 mic3- third negative high impedance input to transmit preamplifier for microphone connection. 6 mbias microphone biasing switch. 7v cca power supply input for the analog section. v cc and v cca can be directly connected together for low cost applications (see STW5093 power supply notes). 8 mic1+ positive high impedance input to transmit pre-amplifier for microphone connection. 9 mic1- negative high impedance input to transmit pre-amplifier for microphone connection. 10 gnda analog ground: all analog signals are referenced to this pin. gnd and gnda can be connected together for low cost applications (see STW5093 power supply notes). 11 mic2+ second positive high impedance input to transmit pre-amplifier for microphone connection. 12 mic2- second negative high impedance input to transmit pre-amplifier for microphone connection. 13 v ccp power supply input for the v fr and v lr drivers. v ccp and v cca must be connected together. 14,15 v lr- , v lr+ receive analog extra amplifier complementary outputs. these outputs can drive directly earpiece transductor of 8 ? or 50nf. the signal at these outputs can be the sum of: - receive speech signal from dr, - internal tone generator, - sidetone signal. 16 gndp power ground. v fr and v lr drivers are referenced to this pin. gndp and gnda must be connected together. 17 v fr receive analog earpiece amplifier output. this output can drive directly earpiece transductor of 30 ? or 50nf. the signal at this output can be the sum of: - receive speech signal from d r , - internal tone generator, - sidetone signal. 18 lo a logic 1 written into do (cr1) appears at lo pin as a logic 0 a logic 0 written into do (cr1) appears at lo pin as a logic 1. 19 bz pulse width modulated buzzer driver output. 20 cclk control clock input: this clock shifts serial control information into ci and out from co when the cs- input is low, depending on the current instruction. cclk may be asynchronous with the other system clocks. 21 cs- chip select input: when this pin is low, control information is written into and out from the STW5093 via ci and co pins. 22 ci control data input: serial control information is shifted into the STW5093 on this pin when cs- is low on the rising edges of cclk. 23 auxclk auxiliary clock input. values must be 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz selected by means of control register cr0. auxclk is not used to shift in and out data .com .com .com .com 4 .com u datasheet
STW5093 4/34 24 vccio power supply input for the digital i/o's. 25 co control data output: serial control/status information is shifted out from the STW5093 on this pin when cs- is low on the falling edges of cclk. 26 gnd ground: all digital signals are referenced to this pin. 27 d x transmit data ouput: data is shifted out on this pin during the assigned transmit time slots. elsewhere dx output is in the high impedance state. in delayed and non-delayed normal frame synchr. modes, voice data byte is shifted out from tristate output dx at the mclk on the rising edge of mclk, while in non-delayed reverse frame synchr mode voice data byte is shifted out on the falling edge of mclk. 28 d r receive data input: data is shifted in during the assigned received time slots in delayed and non-delayed normal frame synchr. modes voice data byte is shifted in at the mclk frequency on the falling edges of mclk, while in non-delayed reverse frame synchr. mode voice data byte is shifted in at the mclk frequency on the rising edges of mclk. 29 fs frame sync input: this signal is a 8khz clock which defines the start of the transmit and receive frames. any of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. 30 mclk master clock input: this signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. values must be 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz selected by means of control register cr0. mclk is used also to shift-in and out data. n pin description pin function (continued) .com .com .com .com 4 .com u datasheet
5/34 STW5093 1.0 functional description 1.1 device operation 1.1.1 power on initialization: when power is first applied, power on reset circuitry initializes STW5093 and puts it into the power down state. gain control registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the control register description section. all codec functions are disabled. the desired selection for all programmable functions may be intialized prior to a power up command using the microwire control channel. note: after register programming, a subsequent activation of the internal power on reset can be detected by programming to 1 the do bit in the cr1 register; this sets to the logic level 0 the lo output. if an internal power on reset occurs, lo automatically switches to logic level 1. 1.1.2 power up/down control: following power-on initialization, power up and power down control may be accomplished by writing any of the control instructions listed in table 1 into STW5093 with "p" bit set to 0 for power up or 1 for power down. normally, it is recommended that all programmable functions be initially programmed while the device is pow- ered down. power state control can then be included with t he last programming instruction or in a separate sin- gle byte instruction. any of the programmable registers may also be modified while STW5093 is powered up or down by setting "p" bit as indicated. when power up or down control is entered as a single byte instruction, bit 1 must be set to a 0. when a power up command is given, all de-activated circuits are activated, but output dx will remain in the high impedance state until the second fs pulse after power up. 1.1.3 power down state: following a period of activity, power down state may be reentered by writing a power down instruction. control registers remain in their current state and can be changed by microwire control interface. in addition to the power down instruction, detection of loss mclk (no transition detected) automatically enters the device in "reset" power down state with dx output in the high impedance state. 1.1.4 transmit section: transmit analog interface is designed in two stages to enable gains up to 42.5 db to be realized. stage 1 is a low noise differential amplifier providing a selectable 0 or 20 db gain via bit 1 (pg) of register cr4. a microphone may be capacitevely connected to mic1+, mic1- inputs, while the mic2+ mic2? and mic3+ mic3- inputs may be used to capacitively connect a second microphone or a third microphone respectively or an auxiliary audio circuit. mic1 or mic2 or mc3 or transmit mute is selected with bits 6 and 7 of register cr4. in the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. following the first stage is a programmable gain amplifier which provides from 0 to 22.5 db of additional gain in 1.5db step. the total transmit gain should be adjusted so that, at refe rence point a, see block diagram description, the in- ternal 0 dbm0 voltage is 0.49 vrms (overload level is 0.7 vrms). second stage amplifier gain can be pro- grammed with bits 4 to 7 of cr5. an active rc prefilter then precedes the 8th order band pass switched capacitor filter. a/d converter can be either a 14-bit linear (bit cm = 0 in register cr0) or c an have a compressing characteristics (bit cm = 1 in reg- ister cr0) according to ccitt a or mu255 coding laws. a precision on chip voltage reference ensures accurate and highly stable transmission levels. any offset voltage arising in the gain-set amplifier, the fi lters or the comparator is cancelled by an internal au- tozero circuit. each encode cycle begins immediatly at the beginning of the selected transmit time slot. the total signal delay referenced to the start of the time slot is approximatively 195 s (due to the transmit filter) plus 125 s (due to encoding delay), which totals 320 s. voice data is shifted out on dx during the selected time slot on the trans- .com .com .com .com 4 .com u datasheet
STW5093 6/34 mit rising edges of mclk in delayed or non-delayed norm al mode or on the falling edges of mclk in non-de- layed reverse mode.a separate mbias output can be used to bias a microphone (bit mb = 1 in register cr10) 1.1.5 receive section: voice data is shifted into the decoder's receive voice data register via the dr pin during the selected time slot on the falling edges of mclk in delayed or non-delayed normal mode or on the rising edges of mclk in non- delayed reverse mode. the decoder consists of either a 14-bit linear or an expand ing dac with a or mu255 law decoding characteristic. following the decoder is a 3400 hz 8th order band-pass switched capacitor filter with integral sin x/x correction for the 8 khz sample and hold. 0 dbmo voltage at this (b) reference point (see block diagr am description) is 0.49 vrms. a transcient suppress- ing circuitry ensure interference noise suppression at power up. the analog speech signal output can be routedeither to earpiece (vfr output) or to an extra analog output (v lr+ , v lr- outputs) by setting bits oe1, oe2, and se (4, 3, and 0 of cr4). total signal delay is approximatively 190 s (filter plus decoding delay) plus 62.5 s (1/2 frame) which gives ap- proximatively 252 s. output vfr is intended to directly drive an earpiece. preceding the outputs is a programmable attenuation am- plifier, which must be set by writing to bits 4 to 7 in register cr6. attenuations in the range 0 to -30 db relative to the maximum level in 2 db step can be programmed. t he input of this programmable amplifier is the sum of several signals which can be selected by writing to register cr4.: - receive speech signal which has been decoded and filtered, - internally generated tone signal, (tone amplitude is programmed with bits 4 to 7 of register cr7), - sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register cr5 v fr is capable of driving output power levels up to 16.5mw into a 30 ? load impedance capacitively connected between v fr+ and gnd. piezoceramic receivers up to 50nf can also be driven. differential outputs v lr+ ,v lr- are intended to directly drive an extra output. preceding the outputs is a program- mable attenuation amplifier, which must be set by writing to bits 0 to 3 in register cr6. attenuations in the range 0 to -30 db relative to the maximum level in 2.0 db step can be programmed. the input of this programmable amplifier can be the sum of signals which can be selected by writing to register cr4: - receive speech signal which has been decoded and filtered, - internally generated tone signal, (tone amplitude is programmed with bits 4 to 7 of register cr7), - sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register cr5. v lr+ and v lr- outputs are capable of driving output power le vel up to140mw into differentially connected load impedance of 8 ? . piezoceramic receivers up to 50nf can also be driven. buzzer output: single ended output bz is intended to drive a buzzer, via an external bjt, with a squarewave pulse width mod- ulated (pwm) signal the frequency of which is stored into register cr8. for some applications it is also possible to amplitude modulate this pwm signal with a squarewave signal hav- ing a frequency stored in register cr9. maximum load for bz is 5k ? and 50pf. 1.1.6 digital interface (fig. 1) f s frame sync input determines the beginning of frame. it may have any duration from a single cycle of mclk to a squarewave. three different relationships may be established between the frame sync input and the first time slot of frame by setting bits dm1 and dm0 in regist er cr1. in non delayed data mode (long frame timing) the first time slot begins nominally coincident with the rising edge of f s . alternative is to use delayed data mode (short frame sync timing) in which fs input must be high at least a half cycle of mclk earlier the frame beginning in the case of linear code (bit cm = 0 in register cr0) the msb is the first bit that is transmitted and received. .com .com .com .com 4 .com u datasheet
7/34 STW5093 in the case of companded code only (bit cm = 1 in register cr0) a time slot assignment circuit on chip may be used with all timing modes, allowing connection to one of the two b1 and b2 voice data channels. two data formats are available: in format 1, time slot b1 corresponds to the 8 mclk cycles following immedi- ately the rising edge of fs, while time slot b2 corres ponds to the 8 mclk cycles following immediately time slot b1. in format 2, time slot b1 is identical to format 1. time slot b2 appears two bit slots after time slot b1. this two bits space is left available for insertion of the d channel data. data format is selected by bit ff (2) in register cr0. time slot b1 or b2 is selected by bit ts (1) in control reg- ister cr1. bit en (2) in control register cr1 enables or disables the voice data transfer on d x and d r as appropriate. dur- ing the assigned time slot, dx output shifts data out from the voice data register on the rising edges of mclk in the case of delayed and non-delayed normal modes or on the falling edges of mclk in the case of non-de- layed reverse mode. serial voice data is shifted into dr input during the same time slot on the falling edges of mclk in the case of delayed and non-delayed normal modes or on the rising edges of mclk in the case of non- delayed reverse mode. d x is in the high impedance tristate condition when in the non selected time slots. figure 1. digital interface format (significant only for companded code) 1.1.7 control interface: control information or data is written into or read-back from STW5093 via the serial control port consisting of control clock cclk, serial data input ci and output co, and chip select input, cs-. all control instructions re- quire 2 bytes as listed in table 1, with the exception of a single byte power-up/down command. to shift control data into STW5093, cclk must be pulsed high 8 times while cs- is low. data on ci input is shifted into the serial input register on the rising edge of each cclk pulse. after all data is shifted in, the content of the input shift register is decoded, and may indicate th at a 2nd byte of control data will follow. this second byte may either be defined by a second byte-wide cs- puls e or may follow the first contiguously, i.e. it is not mandatory for cs- to return high in between the first and second control bytes. at the end of the 2nd control byte, data is loaded into the appropriate programmable register. cs- must return high at the end of the 2nd byte. (non delayed timing) (delayed timing) fs fs x b2 b1 xx b2 b1 mclk dr dx format 1 (non delayed timing) (delayed timing) fs fs x b2 b1 xx b2 b1 mclk dr dx format 2 d98tl394 .com .com .com .com 4 .com u datasheet
STW5093 8/34 to read-back status information from STW5093, the first byte of the appropriate instruction is strobed in during the first cs- pulse, as defined in table 1. cs- must be set low for a further 8 cclk cycles, during which data is shifted out of the co pin on the falling edges of cclk. when cs- is high, co pin is in the high impedance tri-stat e, enabling co pins of several devices to be multi- plexed together. thus, to summarise, 2 byte read and write instructions may use either two 8-bit wide cs- pulses or a single 16 bit wide cs- pulse. 1.1.8 control channel access to pcm interface: it is possible to access the b channel previously select ed in register cr1 in the case of companded code only. a byte written into control register cr3 will be automatically transmitted from dx output in the following frame in place of the transmit pcm data. a byte written into control register cr2 will beautomatical ly sent through the receive path to the receive am- plifiers. in order to implement a continuous data flow from the con trol microwire interface to a b channel, it is nec- essary to send the control byte on each pcm frame. a current byte received on d r input can be read in the register cr2. in order to implement a continuous data flow from a b channel to microwire interface, it is necessary to read register cr2 at each pcm frame. 1.1.9 auxclk usage: the auxiliary clock auxclk is only used to keep active the tone and buzzer generation functions to the ear- piece or to the extra amplifier outputs when the master clock mclk is not available, and there is no voice ac- tivity both in transmit and receive channels. when auxclk is selected, the pcm digital interface is inactive (dx in tristate and dr is not read). the selection between auxclk and mclk is done by bit slc in register cr1the input frequency of auxclk is selected via bits f1 and f0 of register cr0 as for the mclk signal. 1.1.10remocon function: the remocon (remote control) function can be us ed to detect the status of an headset button. the remocon function is enabled by setting bit ren (7 of cr10). if enabled, this function is active also when the STW5093 is in power-down state. at remin input an high level is detected as a non pressed button, while a low level is detected as a pressed button. the "pressed button" information can be treated in 2 ways depending on bit rlm (6 of cr10): if rlm = 0 (transparent mode) the information at remin is seen at remout after a debounce time of 50ms maximum. if rlm = 1 (latched mode) the information stored in bit rdl (4 of cr10) is seen at remout.when a low level at remin is detected rdl is set after a debounce time of 50ms maximum.rdl is reset at power on reset and can also be reset writing cr10. the remout output polarity can be inverted setting bit ro i (5 of cr10):the pressed button information is pre- sented at remout output as a logic 1 if bit roi = 0. if roi = 1 the polarity is inverted. 2.0 programmable functions the programmable functions are configur ed by writing to a number of registers using a 2-byte write cycle. most of these registers can also be read-back for verification. byte one is always register address, while byte two is data. table 1 lists the register set and their respective adresses. .com .com .com .com 4 .com u datasheet
9/34 STW5093 table 1. programmable register intructions notes: 1. bit 7 of the address byte and data byte is always the first bit clocked into or out from: ci and co pins when microwire serial port is enabled. x = reserved: write 0 2. "p" bit is power up/down control bit. p = 1 means power down.bit 1 indicates, if set, the presence of a second byte. 3. bit 2 is write/read select bit. 4. registers cr12, cr13, and cr14 are not accessible. function address byte data byte 76543210 single byte power up/down p x x x x x 0 x none write cr0 p000001xsee cr0 table 2 read-back cr0 p000011xsee cr0 write cr1 p000101xsee cr1 table 3 read-back cr1 p000111xsee cr1 write data to receive path p 0 0 1 0 0 1 x see cr2 table 4 read data from dr p 0 0 1 0 1 1 x see cr2 write data to dx p 0 0 1 1 0 1 x see cr3 table 5 write cr4 p010001xsee cr4 table 6 read-back cr4 p010011xsee cr4 write cr5 p010101xsee cr5 table 7 read-back cr5 p010111xsee cr5 write cr6 p011001xsee cr6 table 8 read-back cr6 p011011xsee cr6 write cr7 p011101xsee cr7 table 9 read-back cr7 p011111xsee cr7 write cr8 p100001xsee cr8 table 10 read-back cr8 p100011xsee cr8 write cr9 p100101xsee cr9 table 11 read-back cr9 p100111xsee cr9 write cr10 p 1 0 1 0 0 1 x see cr10 table 12 read-back cr10 p101011xsee cr10 write cr11 p 1 0 1 1 0 1 x see cr11 table 13 read-back cr11 p101111xsee cr11 write test register cr12 p 1 1 0 0 0 1 x reserved write test register cr13 p 1 1 0 1 0 1 x reserved write test register cr14 p 1 1 1 0 0 1 x reserved .com .com .com .com 4 .com u datasheet
STW5093 10/34 table 2. control register cr0 functions *: state at power on initialization (1): significant in companded mode only table 3. control register cr1 functions *: state at power on initialization (1): significant in companded mode only x: reserved: write 0 76543210 function f1 f0 cm ma ia ff b7 dl 0 0 1 1 0 1 0 1 mclk or auxclk = 512 khz mclk or auxclk = 1.536 mhz mclk or auxclk = 2.048 mhz mclk or auxclk = 2.560 mhz * 0 1 linear code * companded code linear code companed code 0 0 1 1 0 1 0 1 2-complement * sign and magnitude 2-complement 1-complement mu-law: ccitt d3-d4 * mu-law: bare coding a-law including even bit inversion a-law: bare coding 0 1 b1 and b2 consecutive * (1) b1 and b2 separated (1) 0 1 8 bits time-slot * (1) 7 bits time-slot (1) 0 1 normal operation * digital loop-back * 76543210 function dm1 dm0 do mr mx en ts slc 0 1 1 x 0 1 delayed data timing * non-delayed normal data timing non-delayed reverse data timing 0 1 l0 latch set to 1 * l0 latch set to 0 0 1 d r connected to rec. path * cr2 connected to rec. path (1) 0 1 trans path connected to d x * cr3 connected to d x (1) 0 1 voice data transfer disable * voice data transfer enable 0 1 b1 channel selected * b2 channel selected (1) 0 1 mclk master clock and fs frame sync inputs are selected * auxclk auxiliary clock input is selected .com .com .com .com 4 .com u datasheet
11/34 STW5093 table 4. control register cr2 functions (1) significant in companded mode only. table 5. control registers cr3 functions (1) significant in companded mode only. table 6. control register cr4 functions *: state at power on initialization 76543210 function d7 d6 d5 d4 d3 d2 d1 d0 msb lsb data sent to receive path or data received from dr input (1) 76543210 function d7 d6 d5 d4 d3 d2 d1 d0 msb lsb dx data transmitted (1) 76543210 function vs te si oe1 oe2 rte hpb se 0 0 1 1 0 1 0 1 transmit input muted * mic1 selected mic2 selected mic3 selected 0 1 internal sidetone disabled * internal sidetone enabled 0 0 1 1 0 1 0 1 receive output muted * vfr output selected vlr output selected not allowed 0 1 ring / tone to v fr or v lr disabled * ring / tone to v fr or v lr enabled 0 1 receive high pass filter enabled * receive high pass filter disabled 0 1 receive signal to v fr or v lr disabled * receive signal to v fr or v lr enabled .com .com .com .com 4 .com u datasheet
STW5093 12/34 table 7. control register cr5 functions *: state at power on initialization table 8. control register cr6 functions *: state at power on initialization table 9. control register cr7 functions *: state at power on initialization (2): value provided if f1 or f2 is selected alone.if f1 and f2 are selected in the summed mode, f1=0.89 vpp while f2=0.7 vpp. x reserved: write 0 76543210 function transmit amplifier sidetone amplifier 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 lsb 0 db gain * 1.5 db gain in 1.5 db step 22.5 db gain 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 -12.5 db gain * -13.5 db gain in 1 db step -27.5 db gain 76543210 function earpiece ampifier [eara] extra amplifier [exta] 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 lsb 0 db gain * -2 db gain in 2 db step -30 db gain 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain * -2 db gain in 2 db step -30 db gain 76543210 function tone gain f1 f2 sn de attenuation f1 v pp f2 v pp 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 x x 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 0 1 0 1 0 db * -3 db -6 db - 9 db -12 db -15 db -18 db -21 db -24 db -27 db 1.6(2) 0.066 1.26(2) 0.053 0 0 1 1 0 1 0 1 f1 and f2 muted * f2 selected f1 selected f1 and f2 in summed mode 0 1 squarewave signal selected * sinewave signal selected 0 1 normal operation tone / ring generator connected totransmit path * .com .com .com .com 4 .com u datasheet
13/34 STW5093 table 10. control register cr8 functions table 11. control register cr9 functions table 12. control register cr10 functions (*) default values inserted into the register at power on. table 13. control register cr11 functions * state at power on initialization 76543210 function f17f16f15f14f13f12f11f10 msb lsb binary equivalent of the decimal number used to calculate f1 76543210 function f27f26f25f24f23f22f21f20 msb lsb binary equivalent of the decimal number used to calculate f2 76543210 function ren rlm roi rdl pg mb dft hft 0 1 remocon function disabled * remocon function enabled 0 1 remocon output in transparent mode * remocon output in latched mode 0 1 remocon output not inverted * remocon output inverted 0 1 remocon detection latch reset by p * remocon detection latch set by internal logic 0 1 20db preamplifier gain * 0db preamplifier gain 0 1 mbias output disabled * mbias output enabled 0 0 1 1 0 1 0 1 standard frequency tone range * halved frequency tone range doubled frequency tone range forbidden 76543210 function be bi bz5 bz4 bz3 bz2 bz1 bz0 0 1 buzzer output disabled (set to 0) * buzzer output enabled 0 1 duty cycle is intended as the relative width of logic 1 * duty cycle is intended as the relative width of logic 0 msb lsb binary equivalent of the decimal number used to calculate the duty cycle. .com .com .com .com 4 .com u datasheet
STW5093 14/34 control register cr0 first byte of a read or a write instruction to control register cr0 is as shown in table 1. second byte is as shown in table 2. master clock / auxiliary clock frequency selection a master clock must be provided to STW5093 to activate all the functions. in the case mclk is absent, auxclk can be provide to STW5093 for activating tone or buzzer functions only. mclk or auxclk frequency can be either 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz.. bit f1 (7) and f0 (6) must be set during initialization to select the correct internal divider.default value is 512 khz. any clock different from the default one must be selected prior a power-up instruction. coding law selection bits ma (4) and ia (3) permit selection of mu-255 law or a law coding with or without even bit inversion if com- panded code (bit cm = 1) is selected. bits ma(4) and ia(3) permit selection of 2-complement, 1-complement or sign and magnitude if linear code (bit cm = 0) is selected. coding selection bit cm (5) permits selection either of linear coding (14-bit) or companded coding (8-bit). default value is linear coding. digital interface format (1) bit ff(2) = 0 selects digital interface in format 1 where b1 and b2 channel are consecutive. ff=1 selects for- mat 2 where b1 and b2 channel are separated by two bits. (see digital interface format section.) 56+8 selection (1) bit 'b7' (1) selects capability for STW5093 to take into account only the seven most significant bits of the pcm data byte selected. when 'b7' is set, the lsb bit on dr is ignored and lsb bit on dx is high impedance. this function allows con- nection of an external "in band" data generator directly connected on the digital interface. digital loopback digital loopback mode is entered by setting dl bit(0) equal 1. in digital loopback mode, data written into receive pcm data register from the selected received time-slot is read-back from that register in the selected transmit time-slot on d x . no pcm decoding or encoding takes place in this mode. transmit and receive amplifier stages are muted. control register cr1 first byte of a read or a write instruction to contro l register cr1 is as shown in table 1. second byte is as shown in table 3. digital interface timing bit dm1(7) = 0 selects digital interface in delayed timing mode, while dm1 = 1 and dm0 = 0 selects non-delayed normal data timing mode, and dm1 = 1 and dm0 = 1 select s non-delayed reverse data timing mode.default is delayed data timing. (1) significant in companded mode only .com .com .com .com 4 .com u datasheet
15/34 STW5093 latch output control bit do controls directly logical status of latch output lo: ie, a "zero" written in bit do puts the output lo at logical 1, while a "one" written in bit do sets the output lo to zero. microwire access to b channel on receive path (1) bit mr (4) selects access from microwire register cr2 to receive path. when bit mr is set high, data writ- ten to register cr2 is decoded each frame, sent to the receive path and data input at dr is ignored. in the other direction, current pcm data input received at dr can be read from register cr2 each frame. microwire access to b channel on transmit path (1) bit mx (3) selects access from microwire write only register cr3 to dx output. when bit mx is set high, data written to cr3 is output at dx every frame and the output of pcm encoder is ignored. msb is always the first pcm bit shifted in or out of: STW5093. transmit/receive en abling/disabling bit 'en' (2) enables or disables voice data transfer on dx and dr pins. when disabled, pcm data from dr is not decoded and pcm time-slots are high impedance on dx. default value is disabled. b-channel selection (1) bit ts(1) permits selection between b1 or b2 channels. default value is b1 channel. clock selection bit slc(0) allows the selection between mclk and auxclk. default value is mclk. control register cr2(1) data sent to receive path or data received from dr input. refer to bit mr(4) in "control register cr1" para- graph. control register cr3 (1) dx data transmitted. refer to bit mx(3) in "control register cr1" paragraph. control register cr4 first byte of a read or a write instruction to contro l register cr4 is as shown in table 1. second byte is as shown in table 6. (1) significant in companded mode only mu 255 law true a law even bit inversion a law without even bit inversion msb lsb msb lsb msb lsb vin = + full scale 100000001010101011111111 vin = 0v 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vin = - full scale 000000000010101001111111 .com .com .com .com 4 .com u datasheet
STW5093 16/34 transmit input selection mic1 or mic2 or mic3 or transmit mute can be selected with bits 6 and 7 (vs and te). transmit gain can be adjusted within a 22.5 db range in 1.5 db step with register cr5. sidetone selection bit "si" (5) enables or disables sidetone circuitry. w hen enabled, sidetone gain can be adjusted with register (cr5). when transmit path is disabled, sidetone circuit is also disabled. output driver selection bits oe1(4) and oe2(3) provide the selection among the ea rpiece output or the extra amplifier output or both outputs muted.oe1 = 1 and oe2 = 1 is not allowed. ring/tone signal selection bit rte (2) provide select capability to connect on-chip ring/tone generator either to an extra amplifier input or to earpiece amplifier input. receiver high pass filter selection bit hpb(1) provides the selection of the receiver high pass filter cutoff frequency. pcm receive data selection bits "se" (0) provide select capability to connect receiv ed speech signal either to an extra amplifier input or to earpiece amplifier input. control register cr5 first byte of a read or a write instuction to control register cr5 is as shown in table 1. second byte is as shown in table 7. transmit gain selection transmit amplifier can be programmed for a gain from 0db to 22.5db in 1.5db step with bits 4 to 7. 0 dbmo level at the output of the transmit amplifier (a re ference point) is 0.492 vrms (overload voltage is 0.707 vrms). sidetone attenuation selection transmit signal picked up after the switched capacitor low pass filter may be fed back into both receive ampli- fiers. attenuation of the signal at the output of the sidetone attenuator can be programmed from ?12.5db to -27.5db relative to reference point a in 1 db step with bits 0 to 3. control register cr6 first byte of a read or a write instruction to contro l register cr6 is as shown in table 1. second byte is as shown in table 8. .com .com .com .com 4 .com u datasheet
17/34 STW5093 earpiece amplifier gain selection: earpiece receive gain can be programmed in 2 db step from 0 db to -30 db relative to the maximum with bits 4 to 7. 0 dbmo voltage at the output of the amplifier on pin vfr is 0.9825 vrms when 0db gain is selected down to 30.925 vrms when -30db gain is selected. extra amplifier gain selection: extra receive amplifier gain can be programmed in 2 db st ep from 0 db to -30 db relative to the maximum with bits 0 to 3. 0 dbmo voltage on the output of the amplifier on pins v lr+ and v lr- 1.965 vrms when 0 db gain is selected down to 61.85 mvrms when -30 db gain is selected. control register cr7: first byte of a read or a write instruction to contro l register cr7 is as shown in table 1. second byte is as shown in table 9. tone/ring amplifier gain selection output level of ring/tone generator, before attenuation by programmable attenuator is 1.6 vpk-pk when f1 gen- erator is selected alone or summed with the f2 generator and 1.26 vpk-pk when f2 generator is selected alone. selected output level can be attenuated down to -27 db by programmable attenutator by setting bits 4 to 7. frequency mode selection bits 'f1' (3) and 'f2' (2) permit selection of f1 and/or f2 frequency generator according to table 9. when f1 (or f2) is selected, output of the ring/tone is a squarewave (or a sinewave) signal at the frequency selected in the cr8 (or cr9) register. when f1 and f2 are selected in summed mode, output of the ring/tone generator is a signal where f1 and f2 frequency are summed. in order to meet dtmf specifications, f2 output leve l is attenuated by 2db relative to the f1 output level. frequency temporization must be controlled by the microcontroller. waveform selection bit 'sn' (1) selects waveform of the output of the ring/tone generator. sinewave or squarewave signal can be selected. dtmf selection bit de (0) permits connection of ring/tone/dtmf generator on the transmit data path instead of the transmit amplifier output. earpiece or extra receive output feed-back may be provided by sidetone circuitry by setting bit si or directly by setting bit rte in register cr4. loudspeaker feed-back may be provided directly by setting bit rtl in register cr4. control registers cr8 and cr9 first byte of a read or a write instruction to control register cr8 or cr9 is as shown in table 1. second byte is respectively as shown in table 10 and 11. if "standard frequency tone range" is selected, tone or ring signal frequency value is defined by the formula: f1 = cr8 / 0.128 hz .com .com .com .com 4 .com u datasheet
STW5093 18/34 and f2 = cr9 / 0.128 hz where cr8 and cr9 are decimal equivalents of the binary values of the cr8 and cr9 registers respectively. thus, any frequency between 7.8 hz and 1992 hz may be selected in 7.8 hz step. if "halved frequency tone range"is selected, tone or ring signal frequency value is defined by the formula: f1 = cr8 / 0.256 hz and f2 = cr9 / 0.256 hz this any frequency between 3.9hz and 996hz may be selected in 3.9hz step. if "doubled frequency tone range"is selected, tone or ring signal frequency value is defined by the formula: f1 = cr8 / 0.064 hz and f2 = cr9 / 0.064 hz thus any frequency between 15.6hz and 3984hz may be selected in 15.6hz step. table 12 gives examples for the main frequencies usual for tone or ring generation. control register cr10 remocon function enable bit ren(7) enables or disables the remoc onfunction. default value is disabled. remocon mode selection bit rlm(6) is used to select between a transparent pr essed button information and a latched pressed button information at remout. in both cases a debounce circuit (50ms max.) is active. remocon output inversion bit roi(5) is used to invert or not the information at remout. default value is not inverted (i.e. pressed button information is a logic 1 at remout. remocon detection latch bit rdl(4) is set by the internal remocon function logic, after the debounce time, when a low level on remin is detected. it can be reset by the mp writing cr10. preamplifier gain selection bit pg(3) provides the selection between 0db and 20db gain of the preamplifier. default value is 20db. microphone bias disabling/enabling bit mb (2) enables or disables a switch for microphone biasing. default value is disabled. tone frequency range selection bit dft(1) and hft(0) permits the selection among "s tandard frequency tone range" (i.e. from 7.8hz to 1992hz in 7.8hz step), "halved frequency tone range" (i.e. from 3.9hz to 996hz in 3.9hz step), and "doubled frequency .com .com .com .com 4 .com u datasheet
19/34 STW5093 tone range" (i.e. from 15.6hz to 3984hz in 15.6hz step) according to the values described in control reg- ister cr8 and cr9. control register cr11 bit be(7) permits connection of a f1 squarewave pwm ring signal, amplitude modulated or not by a f2 square- wave signal, to buzzer driver output bz. bits bz5 to bz 0 define the duty cycle of the pwm squarewave, accord- ing to the following formula: duty cycle = cr11(5 to 0) x 0.78125% where cr11(5 to 0) is the decimal equivalent of the binary value bz5 to bz0. when be = 1, if bits f1 = 1 and f2 = 0 in register cr7, a f1 pwm ring signal is present at the buzzer output, while if bits f1 = 1 and f2 = 1 in register cr7 the f1 pwm ring signal is also amplitude modulated by a f2 square- wave frequency. bit bi (6) allows to chose the logic level at which the duty cycle is referred: bi = 0 means that duty cycle is intended as the relative width of the logi c1, while bi = 1 means that duty cycle is intended as the relative width of the logic 0. when be = 0 (or during power down) bz = 0 if bi = 0 or bz = 1 if bi = 1. table 14. examples of usual frequency selection (standard frequency tone range) description f1 value (decimal) theoretic value (hz) typical value (hz) error% tone 250 hz tone 330 hz tone 425 hz tone 440 hz tone 800 hz tone 1330 hz 32 42 54 56 102 170 250 330 425 440 800 1330 250 328.2 421.9 437.5 796.9 1328.1 -.00 -.56 -.73 -.56 -.39 -.14 dtmf 697hz dtmf 770 hz dtmf 852 hz dtmf 941 hz dtmf 1209 hz dtmf 1336 hz dtmf 1477 hz dtmf 1633 hz 89 99 109 120 155 171 189 209 697 770 852 941 1209 1336 1477 1633 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 -.24 +.44 -.05 -.37 +.16 -.01 .00 .00 sol la si do re mi flat mi fa fa shar p sol sol sharp la si do re mi 50 56 63 67 75 80 84 89 95 100 106 113 126 134 150 169 392 440 494 523.25 587.33 622.25 659.25 698.5 740 784 830.6 880 987.8 1046.5 1174.66 1318.5 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 -.30 -.56 -.34 +.04 -.23 +.45 -.45 -.45 +.30 -.34 -.29 +.33 -.34 +.04 -.23 +.14 .com .com .com .com 4 .com u datasheet
STW5093 20/34 timing diagram figure 2. non delayed data timing mode (normal) (*) figure 3. delayed data timing mode (*) (*) in the case of companded code the timing is applied to 8 bits instead of 16 bits. .com .com .com .com 4 .com u datasheet
21/34 STW5093 timing diagram figure 4. non delayed reverse data timing mode (* (*) in the case of companded code the timing is applied to 8 bits instead of 16 bits. figure 5. serial control timing (microwire mode) 12345671617 thmfr mclk trm tfm twmm twml thmfr tsfmr 1234567 16 tdmdr tdfd fs dx tdmzr 1234567 16 tsdm thmdr dr d93tl076a .com .com .com .com 4 .com u datasheet
STW5093 22/34 absolute maximum ratings operative supply voltages timing specifications (unless otherwise specified, v ccio = 1.8v to 3.3v ,t amb = -30c to 85c ; typical characteristics are specified at v ccio = 3.0v, t amb = 25 c; all signals are referenced to gnd, see note 5 for timing definitions) notice: all timing specifications can be changed. master clock timing pcm interface timing parameter value unit v cc to gnd 4.6 v voltage at mic (v cc 3.3v) v cc +0.5 to gnd -0.5 v current at v fr and v lr 100 ma current at any digital output 50 ma voltage at any digital input (v ccio 3.3v); limited at 50ma v ccio + 0.5 to gnd -0.5 v storage temperature range - 65 to + 150 c lead temperature (wave soldering, 10s) + 260 c symbol min. max. unit v cc = v cca = v ccp 2.7 3.3 v v ccio 1.8 v cc v symbol parameter test condition min. typ. max. unit f mclk frequency of mclk selection of frequency is programmable (see table 2) 512 1.536 2.048 2.560 khz mhz mhz mhz t wmh period of mclk high measured from v ih to v ih 150 ns t wml period of mclk low measured from v il to v il 150 ns t rm rise time of mclk measured from v il to v ih 30 ns t fm fall time of mclk measured from v ih to v il 30 ns symbol parameter test condition min. typ. max. unit t hmf hold time mclk low to fs low 0 ns t sfm setup time, fs high to mclk low 30 ns t dmd delay time, mclk high to data valid load = 20pf 100 ns .com .com .com .com 4 .com u datasheet
23/34 STW5093 serial control port timing t dmz delay time, mclk low to dx disabled 10 100 ns t dfd delay time, fs high to data valid load = 20pf; applies only if fs rises later than mclk rising edge in non delayed mode only 100 ns t sdm setup time, dr valid to mclk receive edge 20 ns t hmd hold time, mclk low to d r invalid 10 ns t hmfr hold time mclk high to fs low 30 ns t sfmr setup time, fs high to mclk high 30 ns t dmdr delay time, mclk low to data valid load = 20pf 100 ns t dmzr delay time, mclk high to dx disabled 10 100 ns t hmdr hold time, mclk high to d r invalid 20 ns symbol parameter test condition min. typ. max. unit f cclk frequency of cclk 2.048 mhz t wch period of cclk high measured from v ih to v ih 160 ns t wcl period of cclk low measured from v il to v il 160 ns t rc rise time of cclk measured from v i l to v ih 50 ns t fc fall time of cclk measured from v ih to v il 50 ns t hcs hold time, cclk high to cs- low 10 ns t ssc setup time, cs- low to cclk high 50 ns t sdc setup time, ci valid to cclk high 50 ns t hcd hold time, cclk high to ci invalid 50 ns t dcd delay time, cclk low to co data valid load = 20pf 80 ns t dsd delay time, cs-low to co data valid 50 ns symbol parameter test condition min. typ. max. unit timing specifications (continued) pcm interface timing (continued) .com .com .com .com 4 .com u datasheet
STW5093 24/34 note 5: a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purposes of this specification the following conditions apply: a) all input signal are defined as: v il = 0.2v ccio , v ih = 0.8v ccio , t r < 10ns, t f < 10ns. b) delay times are measured from the inputs signal valid to the output signal valid. c) setup times are measured from the data input valid to the clock input invalid. d) hold times are measured from the clock signal valid to the data input invalid. electrical characteristics (unless otherwise specified, v ccio = 1.8v to 3.3v, t amb = -30c to 85c; typical characteristic are specified at v ccio = 3.0v, t amb = 25c ; all signals are referenced to gnd) digital interfaces t ddz delay time cs-high or 8th cclk low to co high impedance whichever comes first 10 80 ns t hsc hold time, 8th cclk high to cs- high 100 ns t scs set up time, cs- high to cclk high 100 ns symbol parameter test condition min. typ. max. unit v il input low voltage all digital inputs except remin dc ac 0.3v ccio 0.2v ccio v v v ih input high voltage all digital inputs except remin dc ac 0.7 vccio 0.8 vccio v v v ilrem input low voltage remin input 0.5 v v ihrem input high voltage remin input 1.4 v v ol output low voltage all digital outputs, i l = 10 a all digital outputs, i l = 2ma 0.1 0.4 v v v oh output high voltage all digital outputs, i l = 10 a all digital outputs, i l = 2ma v ccio -0.1 v ccio -0.4 v v i il input low current any digital input, gnd < v in < v il -10 10 a i ih input high current any digital input, v ih < v in < v ccio -10 10 a i oz output current in high impedance (tri-state) dx and co -10 10 a symbol parameter test condition min. typ. max. unit timing specifications (continued) serial control port timing (continued) .com .com .com .com 4 .com u datasheet
25/34 STW5093 figure 6. a.c. testing input, output waveform analog interfaces symbol parameter test condition min. typ. max. unit r mbias switch resistance for microphone bias mbias 100mv under v cc 150 ? i mic input leakage gnd < v mic < v cc -100 +100 a r mic input resistance gnd < v mic < v cc 50 k ? r lv fr load resistance 30 ? c lv fr load capacitance 50 nf r ovfr0 output resistance steady zero pcm code applied to dr; i = 1ma 1.0 ? r lvlr load resistance v lr+ to v lr- 8 ? c lvlr load capacitance from v lr+ to v lr- 50 nf r olvro output resistance steady zero pcm code applied to dr; i 1ma 1 ? v osvlro differential offset voltage at v lr+ , v lr- alternating zero pcm code applied to dr maximum receive gain; r l = 50 ? -50 +50 mv ac testing: inputs are driven at 0.8v ccio for a logic "1"and 0.2v ccio for a logic "0 ". timing measurements are made at 0.7v ccio for a logic "1"and 0.3v ccio for a logic "0". 0.8v ccio 0.2v ccio 0.7v ccio 0.3v ccio 0.7v ccio 0.3v ccio test points intput/output d93tl077a .com .com .com .com 4 .com u datasheet
STW5093 26/34 transmission characteristics (unless otherwise specified, v cc = 2.7v to 3.3v, t amb = -30c to 85c; typical characteristics are specified at v cc = 3.0v, t amb = 25c, mic1/2/3 = 0dbm0, d r = -6dbm0 pcm code, f = 1015.625 hz; all signal are referenced to gnd) amplitude response (maximum, nominal, and minimum levels) transmit path - absolute levels at mic1 / mic2 / mic3 amplitude response (maximum, nominal, and minimum levels) receive path - absolute levels at v fr amplitude response (maximum, nominal, and minimum levels) receive path - absolute levels at vlr (differentially measured) amplitude response transmit path symbol parameter test condition min. typ. max. unit 0 dbm0 level transmit amps connected for 20db gain 49.26 mv rms overload level 70.71 mv rms 0 dbm0 level transmit amps connected for 42.5db gain 3.694 mv rms overload level 5.302 mv rms symbol parameter test condition min. typ. max. unit 0 dbm0 level receive amp programmed for 0db attenuation 0.9825 v rms 0 dbm0 level receive amp programmed for30db attenuation 30.925 mv rms symbol parameter test condition min. typ. max. unit 0 dbm0 level receive amp programmed for 0db attenuation 1.965 v rms 0 dbm0 level receive amp programmed for 30db attenuation 61.85 mv rms symbol parameter test condition min. typ. max. unit g xa transmit gain absolute accuracy transmit gain programmed for minimum.measure deviation of digital pcm code from ideal 0db m0 pcm code at d x -0.5 0.5 db g xag transmit gain variation with programmed gain measure transmit gain over the range from maximum to minimum setting.calculate the deviation from the programmed gain relative to gxa, i.e. g axg = g actual - g prog. - g xa -0.5 0.5 db g xat transmit gain variation with temperature measured relative to g xa . min. gain < g x < max. gain -0.1 0.1 db g xav transmit gain variation with supply measured relative to g xa g x = minimum gain -0.1 0.1 db .com .com .com .com 4 .com u datasheet
27/34 STW5093 (*) the limit at frequencies between 4600hz and 8000hz lies on a straight line connecting the two frequencies on a linear (db) scale versus log (hz) scale. receive path g xaf transmit gain variation with frequency relative to 1015,625 hz, multitone test technique used.min. gain < g x < max. gain f = 60 hz f = 100 hz f = 200 hz f = 300 hz f = 400 hz to 3000 hz f = 3400 hz f = 4000 hz f = 4600 hz (*) f = 8000 hz (*) -1.5 -0.5 -1.5 -30 -20 -6 0.5 0.5 0.0 -14 -35 -47 db db db db db db db db db g xal transmit gain variation with signal level sinusoidal test method.reference level = -10 dbm0 v mic = -40 dbm0 to +3 dbm0 v mic = -50 dbm0 to -40 dbm0 v mic = -55 dbm0 to -50 dbm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 db db db symbol parameter test condition min. typ. max. unit g rae receive gain absolute accuracy receive gain programmed for maximum apply -6 dbm0 pcm code to dr measure v fr -0.5 0.5 db g ral receive gain absolute accuracy receive gain programmed for maximum apply -6 dbm0 pcm code to dr measure v lr -0.5 0.5 db g rage receive gain variation with programmed gain measure v fr gain over the range from maximum to minimum setting. calculate the deviation from the programmed gain relative to g rae , i.e. g rage = g actual - g prog . - g rae -0.5 0.5 db g ragl receive gain variation with programmed gain measure v lr gain over the range from maximum to minimum setting.calculate the deviation from the programmed gain relative to g ral , i.e. g ragl = g actual - g prog. - g ral -0.5 0.5 db g rat receive gain variation with temperature measured relative to gra. (v lr and v fr ) min. gain < g r < max. gain -0.1 0.1 db symbol parameter test condition min. typ. max. unit amplitude response (continued) transmit path (continued) .com .com .com .com 4 .com u datasheet
STW5093 28/34 g rav receive gain variation with supply measured relative to gra. (v lr and v fr ) g r = maximum gain -0.1 0.1 db g raf receive gain variation with frequency (v lr and v fr ) hpb = 0 relative to 1015,625 hz, multitone test technique used. min. gain < g r < max. gain f = 60hz f = 100hz f = 200 hz f = 300 hz f = 400 hz to 3000 hz f = 3400 hz f = 4000 hz -1.5 -0.5 -1.5 -20 -12 -2 0.5 0.5 0.0 -14 db db db db db db db receive gain variation with frequency (v lr and v fr ) hpb = 1 relative to 1015,625 hz, multitone test technique used. min. gain < g r < max. gain f = 50hz f = 100 hz to 3000 hz f = 3400 hz f = 4000 hz -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 db db db db g ral e receive gain variation with signal level (v fr ) sinusoidal test method reference level = -10 dbm0 d r = -40 dbm0 to -3 dbm0 d r = -50 dbm0 to -40 dbm0 d r = -55 dbm0 to -50 dbm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 db db db g ral l receive gain variation with signal level (v lr ) sinusoidal test method reference level = -10 dbm0 d r = -40 dbm0 to -3 dbm0 d r = -50 dbm0 to -40 dbm0 d r = -55 dbm0 to -50 dbm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 db db db symbol parameter test condition min. typ. max. unit amplitude response (continued) receive path (continued) .com .com .com .com 4 .com u datasheet
29/34 STW5093 envelope delay distortion with frequency noise (*) 300 to 3400hz bandwidth crosstalk symbol parameter test condition min. typ. max. unit dxa tx delay, absolute f = 1600 hz 320 s dxr tx delay, relative f = 500 - 600 hz f = 600 - 800 hz f = 800 - 1000 hz f = 1000 - 1600 hz f = 1600 - 2600 hz f = 2600 - 2800 hz f = 2800 - 3000 hz 290 180 50 20 55 80 180 s s s s s s s dra rx delay, absolute f = 1600 hz 280 s drr rx delay, relative f = 500 - 600 hz f = 600 - 800 hz f = 800 - 1000 hz f = 1000 - 1600 hz f = 1600 - 2600 hz f = 2600 - 2800 hz f = 2800 - 3000 hz 200 110 50 20 65 100 220 s s s s s s s symbol parameter test condition min. typ. max. unit nxp tx noise, p weighted (up to 35db) v mic = 0v, de = 0 -75 -70 dbm0p nrp rx noise, linear weighted (*) (max. gain) receive pcm code = positive zero si = 0 and rte = 0 120 150 vrms nrs noise, single frequency mic = 0v, loop-around measurament from f = 0 hz to 100 khz -50 dbm0 ppsrx psrr, tx mic = 0v, v cc = 3.0 v dc + 50 mvrms; f = 100hz to 50khz 30 db ppsrp psrr, rx pcm code equals positive zero, v cc = 3.0vdc + 50 mvrms, f = 100 hz - 4 khz f = 4 khz - 50 khz 30 30 db db sos spurious out-band signal at the output dr input set to -6 dbm0 pcm code 300 - 3400 hz input pcm code applied at d r 4600 hz - 5600 hz 5600 hz - 7600 hz 7600 hz - 8400 hz -40 -50 -50 db db db symbol parameter test condition min. typ. max. unit c tx-r transmit to receive transmit level = 0 dbm0, f = 300 - 3400 hz d r = quiet pcm code -100 -65 db c tr - x receive to transmit receive level = -6 dbm0, f = 300 - 3400 hz mic = 0v -80 -65 db .com .com .com .com 4 .com u datasheet
STW5093 30/34 distortion (*) the limit curve shall be determined by straight li nes joining successive coordinates given in the table. (#) lower limits used during the automatic te sting to avoid unrealistic yield loss due to ?2db imprecision of time-limited nois e measurements. power dissipation symbol parameter test condition min. typ. max. unit s tdx (*) signal to total distortion (up to 35db gain) typical values are measured with 30.5db gain sinusoidal test method (measured using linear 300 to 3400 weighting) level = 0 dbm0 level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 56 50 48 43 38 29 24 15 # 56 50 48 43 37.5 28.5 23 13 65 64 61 52 42 31 26 16 db db db db db db db db s dfx single frequency distortion transmit 0 dbm0 input signal -80 -56 db s tdre (*) signal to total distortion (v fr ) ( up to 20db attenuation) typical values are measured with 20db attenuation. sinusoidal test method (measured using linear 300 to 3400 weighting) level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 50 48 43 38 29 24 15 64 62 53 43 33 28 18 db db db db db db db s dfr single frequency distortion receive (v fr ) -6 dbm0 input signal -80 -50 db s tdrl (*) signal to total distortion (v lr ) (up to 20db attenuation) typical values are measured with 20db attenuation sinusoidal test method (measured using linear 300 to 3400 weighting) level = -6 dbm0 level = -10 dbm0 level = -20 dbm0 level = -30 dbm0 level = -40 dbm0 level = -45 dbm0 level = -55 dbm0 50 48 43 38 29 24 15 64 62 53 43 33 28 18 db db db db db db db s dlr single frequency distortion receive (v lr ) -6 dbm0 input signal -80 -50 db md intermodulation loop-around measurement voltage at mic = -10 dbm0 to -27 dbm0, 2 frequencies in the range 300 - 3400 hz -75 -46 db symbol parameter test condition min. typ. max. unit i cc0 power down current cclk,ci = 0.1v; cs- = v ccio -0.1v remocon function disabled (ren = 0) 0.4 5 a i cc0r power down current cclk,ci = 0.1v; cs- = v ccio -0.1v remocon function enabled (ren = 1) remin = v ilrem or remin = v ihrem 210 a i cc1 power up current v lr+ , v lr- and v fr not loaded 5 8 ma .com .com .com .com 4 .com u datasheet
31/34 STW5093 audio codec applications figure 7. application note for microphone connections. figure 8. application note for v lr connections. figure 9. application note for v fr connections. 1k ? 2k ? 22 f 0.47 f 0.47 f 4k ? 4k ? mbias micp micn STW5093 d98tl395 single ended mode 1k ? 2k ? 22 f 0.47 f 0.47 f 4k ? 4k ? mbias micp micn STW5093 d98tl396 1k ? differential mode r r v lr+ v lr- STW5093 d98tl397a ep r must be greater then 50 ? for hi g hes ca p acitor transducers, lower r values can be used ceramic receivers (50nf) v lr+ v lr- STW5093 d98tl398 ep dynamic receivers (8 ? ) r v fr STW5093 d98tl409a ep r must be greater then 50 ? for hi g hes ca p acitor transducers, lower r values can be used ceramic receivers (50nf) v fr STW5093 d98tl410 ep dynamic receivers (30 ? ) c=100 f .com .com .com .com 4 .com u datasheet
STW5093 32/34 power supply notes two different strategies can be used to minimize power supply noise/interference. a) recommended strategy: keep analog and digital power supply rails separate. this requires to use two sets of capacitors, one from avcc to agnd and the other from dvcc to dgnd. figure 10. b) low cost strategy: tie analog and digital power supplies t ogether as close as possible to gnd and vcc pins. this allows to use only one set of capacitors between vcc and gnd. figure 11. vccp STW5093 d98tl412 100nf 10 f avcc vcca gndp gnda gnd 100nf agnd agnd dgnd dvcc agnd dgnd vcc vccp STW5093 d98tl413 10 f vcca gndp gnda gnd 100nf vcc .com .com .com .com 4 .com u datasheet
33/34 STW5093 dim. mm inch min. typ. max. min. typ. max. a 1.10 0.043 a1 0.05 0.15 0.002 0.006 a2 0.85 0.90 0.95 0.033 0.035 0.037 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 7.70 7.80 7.90 0.303 0.307 0.311 e 6.40 0.252 e0.50 0.0197 e1 4.30 4.40 4.50 0.169 0.173 0.177 l 0.50 0.60 0.70 0.020 0.024 0.028 k 0? (min.) 8? (max.) tssop30 (thin shrink) c e1 k a b e d e pin 1 identification 15 30 16 tsso30m gage plane 0.25mm l 0.010 mm a1 seating plane 0.004 inch seating plane a2 a1 outline and mechanical data .com .com .com .com 4 .com u datasheet
information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 34/34 STW5093 .com .com .com 4 .com u datasheet

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